1. Technical Field
Embodiments described herein relate to semiconductor devices and methods for semiconductor device design. More particularly, some embodiments disclosed herein relate to methods of assigning spare cells on a semiconductor device based upon the distribution of cell types adjacent to the spare cells.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications. An integrated circuit (IC) chip can be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate. An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells.
Additional spare gates (standard cells) are inserted in VLSI designs (semiconductor chips) in pre-determined locations of the floorplan database for each block. The types of spare cells are also pre-determined (to cover a certain percentage/ratio of various logic cell types). Typically during the floor planning step or initial setup of the floorplan database of the design process, spare cells are inserted to cover the entire floorplan database. These spare cells are used later in the project phase to either perform very late ECOs (Engineering Change Orders) using these cells and reconnecting the wires OR after initial tape-out to make ‘metal only’ type of ECO/fixes for bugs and/or speed paths and/or race conditions.
The observation here is that by inserting a pre-determined set of types of logic cells, one does not have the right ‘type’ of cells in many cases to implement complex ECOs in certain parts of the design because certain parts of the design may use a certain (or certain types) of logic cells more than others.